1. Field of Invention
This invention relates to a semiconductor process and a semiconductor structure for a memory array with buried digit lines (BDL).
2. Description of Related Art
A typical memory array, such as a DRAM or flash memory array, includes word lines and bit lines crossing the word lines, and may utilize vertical MOS transistors to achieve 4F2 cells. For the 4F2 cell, the BDL design is important, wherein each buried digit line in the substrate is coupled to a digit-side junction (source) that acts as a part of a vertical MOS transistor.
FIG. 1 illustrates a conventional process of forming digit-side junctions of BDL-type memory array. A plurality of deep trenches 110 are formed in a substrate 100, a plurality of doped regions 120 are formed in the substrate 100 near the bottom of the trenches 110, and the substrate 100 is subjected to a long drive-in step to drive the doped regions 120 into larger digit-side junctions 130 that overlap with the word lines 140 formed subsequently. Due to the long drive-in step, the junction depth increases significantly and causes at least the issues below: difficulty in the digitline-to-digitline separation, and higher digitline capacitance due to the taller junctions.